RISC-V SoCs from Inception to Tapeout

Course 298

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In the realm of modern System-on-Chips (SoCs), the microprocessor stands as a cornerstone component. This 5-day course delves into the intricacies of microprocessor architecture and internal design, with a particular focus on the innovative concept of Open-Source Instruction Set Architecture (ISA). The course employs RISC-V as a prominent example of contemporary microprocessors, providing participants with a comprehensive understanding of its architecture and ecosystem.

By the end of the course, participants will emerge with a nuanced understanding of microprocessor architecture, an appreciation for the open ISA paradigm, and practical skills in using RISC-V to architect and build sophisticated SoCs. This course empowers individuals to navigate the evolving landscape of microprocessor technology in the context of SoCs, fostering innovation and proficiency in modern computing systems.

Learning objectives

Upon completing the course you will be able to:

Get introduced to fundamentals of microprocessor architectures. - Understand the concept of open ISA. - Understand the ecosystem of RISC-V. - Learn how to use RISC-V to build an SoC that contains CPU, accelerators, peripherals


Day 1: Module-I: Fundamentals:

Microprocessor Design.
Opensource Instruction Set Architecture (ISA).
Different RISC-V Cores.
RISC-V tool chain

Day 2 & 3: Module-II: Chipyard Framework:

What is Chipyard?
How to use Chipyard to design an SoC.
Available cores and how to instantiate them.
On-chip and off-chip communication protocols in Chipyard.

Day 4 & 5: Module-III: SoC Design:

How to choose your core.
Bus systems and on-chip communications.
Off-chip communications (standards, recommendations).
Chip level planning (on-chip communication, Clocking and synchronization, I/O planning, off-chip communication).
Planning for testing and PCB design.
Preparing for your tapeout.