Digital SoC Design: From RTL to GDSII

Course 297

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The digital design flow is a complex process, involving numerous steps to transition a design from RTL to functional silicon in ASICs. This 5- day course aims to demystify this intricate field, providing participants with an in-depth understanding of the diverse transformations occurring at each design step. The focus is on comprehending how these transformations impact final performance metrics and how to fine-tune the process to align with design specifications.

Specifically, the course delves into fundamental elements of the ASIC design process, encompassing HDL modeling, event-driven simulation, synthesis, timing analysis, technology files, standard cell views, physical design, signoff checks, and test planning. Attendees explore the nuances of these elements within the context of ASIC platforms, with multiple tool flow options for learning synthesis, physical design, and signoff.

Throughout the training, participants engage in a comprehensive demonstration project, progressively developed to provide hands-on experience tailored to the ASIC design flow. As an option, attendees may participate in a full tapeout process, guiding them from the initial design phase to the release of GDSII, ready for fabrication. The primary goal of this course is to equip attendees with a profound understanding of ASIC digital flows, supported by practical insights into the industry-standard tools used in ASIC design.

Learning objectives

Upon completing the course you will be able to:

“Holistically Understand” digital design flow (from the specification phase to the signoff checks). - Learn all transformations occur during the design flow and analyze their effect on performance metrics. - Gain knowledge on different technology files and standard cell views. - Clearly define the steps of the design flow, and the use of technology files and standard cells view in each step. - Understand timing-analysis and timing-closure in different design phases. - Understand chip level planning (Power Distribution Network, IO, Global Signals, etc). - Design meaningful digital blocks starting from RTL and taking them to GDSII.


Day 1: Module-I: Fundamentals:

Digital IC design: Introduction, Evolution and Future
Architecture of digital circuits (data path, control path, synchronization, data encoding).
Digital System Design (Microprocessors, FPGA, ASIC).
Fundamentals of digital design (HDL modeling, synthesis , timing analysis and timing closure, physical design, chip planning, signoff checks)

Day 2 & 3: Module-II: ASIC based design:

Components of process design kits (PDKs).
What are standard cells and standard cell views?
Types of digital synthesis.
Timing analysis (STA, SSTA).
Physical design (floorplanning, power planning, Clock Tree Synthesis (CTS), and timing closure)
Chip level planning (I/O, power planning, chip testing)
Signoff checks (DRC, LVS, ..)
Preparing for chip testing, Dos and Don’ts.

Day 4 & 5: Module-III: Hands-on Practice:

Design a Microprocessor as the course final project.
Walkthrough the different steps of both front-end and back-end flow.
Finalize the processor GDSII and perform signoff checks.
All steps will be done using opensource tools and PDKs.
Optional: Tapeout the processor and receive your silicon chip.