Smartphone RF Architecture Fundamentals

Course 267

 Request information about bringing this course to your site.

 Aug 23-Aug 24, 2017 -  San Jose, CA / Rick Fornes

$1,295 until 07/26/2017, then $1,495

  Register now! or Save a seat

Summary

The fourth generation wireless communication systems have been deployed or are soon to be deployed in many countries. However, with an explosion of wireless mobile devices and services, there are still some challenges that cannot be accommodated even by 4G, such as the spectrum crisis and high energy consumption. Wireless system designers have been facing the continuously increasing demand for high data rates and mobility required by new wireless applications and therefore have started research on fifth generation wireless systems that are expected to be deployed beyond 2020. Future challenges facing these potential technologies are the significant increase in the complexity of RF cellular handset communication systems that use massive MIMO and cognitive radio networks.

This course is intended for design, application and test engineers as well as technicians wanting to learn about the fundamentals of handset RF architectures, including aspects of the radio design covering the entire signal chain from the RF input to the A/D Digital interface. The aim is understand system design methods to dissect the different radio architectures with emphasis on the physical layer (RF) for the most advanced commercial 4G-LTE and the new MIMO-5G systems.

Learning objectives

Upon completing the course you will be able to:

  • Gain in-depth understanding of The trade-offs between Digital Modulation Techniques and RF Performance and how this relates to system level performance metrics (e.g. C/No, BER, EVM)
  • Interpret key RF parameters such as Noise figure (NF), Sensitivity, Spurious free Dynamic range, Intermodulation distortion, Calculations - P1dB - IM2 - IP2 - IM3 - IP3 - Cascaded IIP3, Power Added Efficiency (PAE), Adjacent Channel Leakage Ratio (ACLR), Peak-to-Average Power Ratio (PAPR)
  • Understand the trade-offs between block-level performance, choice of radio architectures and overall system performance (e.g. power, area and cost) in relation to a given communication standard
  • Appreciate the improved performance offered by MIMO techniques, advanced RF front ends and Smart Antenna Solutions.

Target Audience

RF and baseband IC engineers, system architects, test and product engineers. Technical managers who would like to get exposure to RF smartphone technology.

Outline

Day One

Cellular Architecture Evolution
 • The 1G to 5G Evolution • Performance Comparisons • Architectures Differences • Key technologies for wireless networks • Advantages and disadvantages of high frequency networks for high speed data transmissions
Key Digital System Requirements for RF Handsets
 • Why Digital • Defining Performance Standards • Bit Error Rate (BER) and Block Error rate (BLER) • Data rates, symbol rates, Eb/No and C/N ratios Vs proportional Fairness Scheduling • The trade-offs between Digital Modulation Techniques and RF performance
Key RF System Requirements for RF Handsets
 • Noise figure (NF) • Sensitivity • Spurious free Dynamic range • Intermodulation distortion • Calculations - P1dB - IM2 - IP2 - IM3 - IP3 - Cascaded IIP3 • Phase noise vs. jitter • Phase noise definition • RMS phase error and EVM • Impact of RMS phase error on BER • Power Added Efficiency (PAE) • Adjacent Channel Leakage Ratio (ACLR) • Peak-to-Average Power Ratio (PAPR)

Day Two

Transceiver Architectures and Integration Techniques
 • Distributed antenna arrays- massive MIMO systems • Ultra-Wideband (UWB) Cellular Architectures • MM-Wave communications • Handset architectures structures • Transceiver designs - Heterodyne receiver - Image reject receiver - Homodyne receiver quadrature mixing and DC offset - Tracking Receivers - transmitter architectures - spectrum mask
The future of RFIC’s in Handsets
 • MIMO systems • Frequency usage limitations (GaAs-CMOS-LDMOS-GaN-SiGe) • Promising RFIC technologies for 5G • Highly integrated single chip front end IC’s based on the SiGe BiCMOS process