Frequency Synthesis and Phase-Locked Loop Design

Course 052

San Jose, CA	Dec 08-Dec 10, 2010
Course 052-4320	Presented by Eric Drucker
Register by 11/1/2010 and pay $1395, otherwise pay $1495

Request an onsite quote for this course

Summary:

This three-day course provides both the theoretical and practical knowledge necessary to design frequency synthesis circuits and systems using phase-locked loops and related technologies.

Learning Objectives:

Upon completing the course, the participant will be able to:

• Describe the theory of operation for PLLs and related components.
• Analyze how PLL performance impacts system performance.
• Develop and explain designs of PLL components including mixers, phase detectors, oscillators, and dividers.
• Examine limitations of real world components, design tradeoffs and their effect on PLL performance.
• Develop and explain more advanced frequency synthesis systems designs.
• Test PLL circuits and systems to verify design integrity.

Target Audience:

Engineers designing or specifying PLL frequency synthesis circuits and systems will benefit from this course. Prerequisites include basic digital circuit design, solid analog design skills including transfer functions, basic control and communication theories, and practical experience using PSPICE and/or MATHCAD, and modern RF/analog test equipment and construction methods.

Outline:

Day One
Frequency Synthesis
• History from test and measurement perspective • Direct and indirect frequency synthesizers • Performance requirements
PLLs: Basic Model and Analysis
• Laplace transfer function and linear model; loop types and properties • Loop filters • Open and closed loop gain; Bode plots; phase and gain margin; stability • Calculation of transfer functions and time domain response • Frequency modulation (FM) • Acquisition, lock and hold in range, small signal switching speed • Sampling and Z transforms • Nonlinear modeling/simulation
• Analyses and simulations of all PLL concepts using Mathcad and PSPICE

Day Two
Phase Noise and Spurs
• Phase noise types and graphs • Effects on system performance • Modeling PLL noise performance using Mathcad and PSPICE • Spur types, reduction methods
Phase Detectors
• Mixer • Sample and hold, microwave samplers • Digital and interface to analog circuitry • Commercial product examples
Dividers
• Pre-scalers: silicon, GaAs, and dual and multiple modulus • Pulse swallowing counters in conjunction with dual modulus pre-scalers • Noise, limitations, other issues
Oscillators
• Feedback and negative resistance models • Resonator types • Modeling and predicting phase noise from crystal oscillations • Crystals and crystal oscillators • Oscillator design using PSPICE and Compact

Day Three
Fractional N Loops
• Implementation techniques • Fractional N beyond loop bandwidth • Analog and digital methods for fixing fractional N spurs
Direct Digital Synthesis (DDS)
• Theory, errors and limitations • Commercial products • Incorporating DDS in PLLs
More Complex Loops
• Single sideband mixer/fractional N loop • Multiple (sum and step) loops • Heterodyning and mixing • Reducing oscillator phase noise using delay line methods • Increasing frequency range
Testing
• Phase noise • Switching speed • Loop dynamics • Real world test data

Subject Areas Covered

PLL/Frequency Synthesis Design

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